VPR：一種新的包裝，布局和布線工具的FPGA研究

VPR：一種新的包裝，布局和布線工具的FPGA研究(中文5200字,英文4100字)
摘 要
我們描述了一個基于FPGA新的功能和CAD工具使用的算法，各種途徑和方（VPR）。在減少路由面積計算方面，VPR優于所有的FPGA布局布線工具，我們可以比較。雖然常用的算法是基于已知的方法，是我們目前而言改善運行時間和質量的幾個有效方法。我們目前的版圖和路由上的大型電路的一套新的結果，讓未來的基準電路尺寸上的設計方法更多，用于今天的典型的FPGA布局布線工具工業品外觀設計。VPR是針對一個范圍廣泛的FPGA架構的能力，并且源代碼是公開的。它和相關的網表翻譯/群集工具VPACK已經被用在世界各地的一些研究項目，并且是有用的FPGA體系結構的研究。
VPR: A New Packing， Placement and Routing Tool for
FPGA Research
Department of Electrical and Computer Engineering， University of Toronto
Toronto， ON， Canada M5S 3G4 {vaughn， jayar}@eecg.toronto.edu
Abstract
We describe the capabilities of and algorithms used in a new FPGA CAD tool，Versatile Place and Route (VPR). In terms of minimizing routing area， VPR outperforms all published FPGA place and route tools to which we can compare.Although the algorithms used are based on previously known approaches， we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today’s industrial designs.VPR is capable of targeting a broad range of FPGA architectures， and the source code is publicly available. It and the associated netlist translation /clustering tool VPACK have already been used in a number of research projects worldwide， and should be useful in many areas of FPGA architecture research.